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HCLTech

Design and Verification Engineer

HCLTech

Hyderabad, Telangana, India · पूरा समय

अप्लाय करने वाले प्रथम बनिए

अनुभव
7–10 yrs
वेतन
उद्घाटन
1
की तैनाती
2 पहले
कार्य मोड
कार्यालय में हूँ
शिक्षा
Any graduate
Eligibility
Any graduate.
Resume
Required to apply

Where you'll work

नौकरी का विवरण

Job summary

We are looking for an experienced Design Verification Engineer to strengthen our team and help validate the quality and behavior of advanced ASICs and SoCs. The role calls for a strong command of verification approaches and the ability to manage demanding verification work. You will contribute to building solid verification plans and environments that support the successful delivery of next-generation integrated circuits.

What you will do

  • Create and execute detailed verification plans using modern methodologies such as UVM and formal verification.
  • Build robust verification environments and testbenches that drive high code coverage.
  • Use simulation and formal tools to validate RTL behavior thoroughly.
  • Troubleshoot verification issues, trace failures to the root cause, and help close design problems.
  • Work closely with RTL design engineers to speed up bug fixes and stay aligned with the verification plan.
  • Guide and support junior Design Verification engineers while encouraging teamwork and knowledge sharing.
  • Take part in code reviews and promote strong verification coding practices.
  • Keep up to date with evolving verification tools, flows, and methodologies.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline; a master’s degree is an added advantage.
  • 7 to 10 years of hands-on experience in Design Verification for ASIC or SoC projects.
  • Strong understanding of core digital design concepts, including combinational logic, sequential logic, and finite state machines.
  • Ability to design, debug, and improve complex verification environments effectively.
  • Solid experience with Verilog or VHDL and a good grasp of verification methods such as UVM and formal verification.
  • Working knowledge of simulation platforms such as ModelSim, Cadence Incisive, or Synopsys VCS, along with scripting in Python or Perl.
  • Prior exposure to formal verification tools and techniques will be considered an advantage.
  • Strong analytical thinking, problem-solving ability, and close attention to detail.
  • Good communication, collaboration, and leadership skills for working within and guiding a team.

Benefits

  • Competitive compensation and benefits aligned with experience.
  • Chance to contribute to advanced, high-impact technology projects.
  • Supportive and collaborative work culture with continuous learning opportunities.
  • Potential for career growth and professional development.

Eligibility

Any graduate can apply.

Additional information

This position is based in Hyderabad, India. The role is for a full-time opportunity. No stipend or salary figure was specified in the source, and no vacancy count, start date, duration, or application deadline was provided. The posting also mentions that the organization is a global technology company with a strong focus on innovation, customer relationships, diversity, social responsibility, sustainability, and education initiatives.

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